1. Field of the Invention
The present invention pertains to a technology for designing a semiconductor integrated circuit using a computer system. In particular, the present invention pertains to a computer-implemented method, an apparatus and a program for designing a semiconductor integrated circuit in consideration of process variations when designing the semiconductor integrated circuit by the use of an Electronic Design Automation (EDA) tool.
2. Description of the Related Art
In designing a semiconductor integrated circuit, it is necessary to control the time (signal propagation delay time), that a signal takes to propagate from a signal input terminal called a source, to a signal output terminal called a sink, of all the signal paths of the circuit via wirings and devices, within a required range.
On the other hand, as the semiconductor integrated circuit has been more finely patterned, so process variations in manufacturing further affect circuit delay characteristics. For example, the delay time T of a gate can be simply expressed by a product Ron×C of on-state resistance Ron and capacitance C, and if a polysilicon gate length W and a channel length L are changed slightly in size during a process, they affect the performance of a cell.
In a design technology in the related art, the effects of such process variations have been taken into account (for example, by making one parameter Kp typify process variation relating to the polysilicon gate length W, and by multiplying the delay time T of the gate by the parameter Kp), in designing the semiconductor integrated circuit. The parameter Kp has been set under the worst condition based on an experimental value.
However, in the related art, for example, the gate length W was comparatively large with respect to the variation of the gate length W, so that the effect of the process variation could be allowed by multiplying the delay time T of the gate by the parameter Kp, as described above, but as the circuit has been more finely pattered and further speeded up, so there is little allowance left for the effect of the process variation.
Further, as the ratio of a wiring delay in circuit delay characteristics increases with finer patterning in a semiconductor process, so the effect of process variation relating to a wiring layer cannot be neglected. This is because the delay caused by wiring becomes larger than the inner delay of a cell and occupies a major portion of the total path delay.
Therefore, it is necessary to take into account, even during the steps of designing, the effect of fluctuations in the wiring capacitance C and the wiring resistance R caused by the process variations, but at present there are no such design techniques or a technical guidelines.